Título

On the characterization of the trapped charge in FG-CMOS inverters

Autor

JESUS EZEQUIEL MOLINAR SOLIS

RODOLFO ZOLA GARCIA LOZANO

IVAN RODRIGO PADILLA CANTOYA

ALEJANDRO DIAZ SANCHEZ

JOSE MIGUEL ROCHA PEREZ

Nivel de Acceso

Acceso Abierto

Licencia

http://creativecommons.org/licenses/by-nc-nd/4.0

Materias

Neuron-MOS - (NEURON-MOS) vMOS - (VMOS) Floating-gate transistors - (FLOATING-GATE TRANSISTORS) CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA - (CTI) FÍSICA - (CTI) ELECTRÓNICA - (CTI)

Resumen o descripción

In this work, an experimental comparison between measured FG CMOS inverters using the quasifloating gate (QFG) and layout-based (L-b) techniques for charge removal in the Floating-gate (FG) and simulations through PSpice is presented. The experiment was developed through the measurements of 40 different IC’s with a total of 200 FG and QFG CMOS inverters characterized on AMI C5FN 0.5 lm technology. The data obtained shows that the layout-based technique reduces the initial charge present at the FG, but presents a very small residual charge. Nevertheless, the offset associated to the charge follows a normal distribution and is predictable. Comparison between measured QFG inverters and simulations shows that the high resistance parasitic diode must be modeled accurately for a proper simulation.

Editor

Springer Science+Business Media

Fecha de publicación

2009

Tipo de publicación

Artículo

Versión de la publicación

Versión aceptada

Recurso de información

http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1229

Formato

application/pdf

Idioma

Inglés

Audiencia

Estudiantes

Investigadores

Público en general

Sugerencia de citación

Molinar-Solis, J.E., et al., (2009). On the characterization of the trapped charge in FG-CMOS inverters, Analog Integr Circ Sig Process (61): 191–198

Repositorio Orígen

Repositorio Institucional del INAOE

Descargas

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