Título
New strategies to improve offset and the speed–accuracy–power tradeoff in CMOS amplifiers
Autor
CARLOS MUÑIZ MONTERO
ALEJANDRO DIAZ SANCHEZ
JOSE MIGUEL ROCHA PEREZ
Nivel de Acceso
Acceso Abierto
Materias
Resumen o descripción
Four continuous-time strategies to improve the
speed–accuracy–power tradeoff in CMOS amplifiers by
using low-power offset-compensation circuits are presented.
The offset contribution at the output voltage is
extracted and used to modify the DC component of the
input voltage or the value of the active load, through low
frequency feedback loops, which are realized using two
transistors operating in weak inversion and a small
capacitor. Because these circuits do not affect the bandwidth
and allow using small transistors, the power consumption
is greatly reduced with respect to an
uncompensated amplifier of the same speed and offset
behavior. The proposed strategies present reduced costs in
area, power consumption and complexity, and a decrease in
the low frequency noise contributions. MonteCarlo,
HSPICE simulations results of common source, class AB
and fully differential amplifiers, and experimental results of
a class AB amplifier, all implemented in a 0.5-lm CMOS
technology are shown. Statistical analyses of these strategies
are also presented. Improvements up to 99.74% and
398.6% in the offset and the power consumption are
respectively observed.
Editor
Springer
Fecha de publicación
julio de 2007
Tipo de publicación
Artículo
Versión de la publicación
Versión aceptada
Recurso de información
Formato
application/pdf
Idioma
Inglés
Audiencia
Estudiantes
Investigadores
Público en general
Sugerencia de citación
Jose Miguel Rocha-Pérez
Repositorio Orígen
Repositorio Institucional del INAOE
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