Author: MONICO LINARES ARANDA

CMOS full-adders for energy-efficient arithmetic applications

MARIANO AGUIRRE HERNANDEZ MONICO LINARES ARANDA (2011)

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

Article

Arithmetic Full-adder High-speed Low-power CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA FÍSICA ELECTRÓNICA ELECTRÓNICA

A design-oriented methodology for accurate modeling of on-chip interconnects

OSCAR GONZÁLEZ DÍAZ MONICO LINARES ARANDA Reydezel Torres Torres (2011)

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.

Article

ABCD matrix De-embedding procedure Interconnection lines Lumped equivalent circuit Distributed equivalent circuit Modeling S-parameters VLSI circuits CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA FÍSICA ELECTRÓNICA ELECTRÓNICA

Circuito de recuperación de reloj CMOS completamente integrable, diferencial, de alta velocidad y bajo consumo de potencia

A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

FRANCISCO RUBEN CASTILLO SORIA MONICO LINARES ARANDA MANUEL SALIM MAZA (2007)

En los sistemas electrónicos de recuperación de información (discos duros, unidades de lectura y escritura de

DVD y CD, etc.), así como en las comunicaciones digitales en banda base, los circuitos de recuperación de

reloj (CRC) juegan un papel fundamental, extrayendo la señal de reloj implícita en los datos recibidos, dicha

señal es necesaria para sincronizar el procesamiento posterior de la información. En la actualidad esta tarea

es difícil de lograr, no solo por la naturaleza aleatoria de los datos, sino por su alta velocidad de transferencia.

En este artículo se presenta el diseño de un circuito de recuperación de reloj integrable en tecnología

CMOS de alto desempeño, que opera a 1.2Gbps y consume únicamente 17.4mW de una fuente de 3.3V.

Las altas prestaciones se logran al realizar un diseño completamente diferencial, utilizando arquitectura PLL

convencional, lógica en modo corriente, así como un novedoso oscilador controlado por voltaje (VCO) de

anillo de solo dos etapas. El diseño fue realizado con parámetros de proceso CMOS AMS de 0.35μm. Los

resultados de la simulación en Hspice comprueban el buen desempeño del circuito, logrando la adquisición

en menos de 300ns.

The clock recovery circuit (CRC) plays a fundamental role in electronic information recovery systems (hard disks,

DVD and CD read/writeable units) and baseband digital communication systems in recovering the clock signal

contained in the received data. This signal is necessary for synchronising subsequent information processing.

Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This

paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC) working

at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially

designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL),

current mode logic (MCML) and a novel two stage ring-based voltage controlled oscillator (VCO). The design

used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance,

achieving tracking in less than 300 ns.

Article

Circuito recuperador de reloj Lógica MCML Oscilador de anillo PLL VCO Clock recovery circuit MCML logic Ring oscillator CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA FÍSICA ELECTRÓNICA

Sincronización de circuitos integrados complejos CMOS

MONICO LINARES ARANDA OSCAR GONZÁLEZ DÍAZ Manuel Salím Maza (2011)

Debido a la tendencia de integrar diversos subsistemas electrónicos y mecánicos complejos en un solo circuito integrado, es necesario alternativas de temporización y sincronización eficientes en velocidad, consumo de potencia y área. En este artículo se propone el uso de osciladores de anillo interconectados y acoplados como redes de generación y distribución de señales de reloj, para la sincronización de sistemas integrados en un mismo chip. Se presentan resultados de simulación HSPICE de redes convencionales y no convencionales diseñadas utilizando parámetros típicos de dos procesos de fabricación de circuitos integrados CMOS pozo N Austria Micro Systems (AMS) 0.35 μm y Berkeley 0.13 μm. En base a resultados experimentales obtenidos de redes de distribución de reloj locales y globales fabricadas con el proceso CMOS de 0.35 μm de AMS, se demuestra que los anillos interconectados y acoplados representan una aproximación apropiada para sistemas integrados en un solo circuito de silicio debido a su buen desempeño, escalabilidad con la tecnología, bajo corrimiento al reloj, alta velocidad, tolerancia a fallas y robustez a variaciones del proceso de fabricación.

Due to the trend of integrating various complex electronic and mechanical subsystems in a single integrated circuit or chip, timing and synchronization alternatives efficient in speed, power consumption, and area are needed. In this paper, the use of interconnected and coupled ring oscillators as clock generation and distribution networks for the synchronization of integrated systems in a single chip is proposed. The HSPICE simulation results of the conventional and no-conventional networks designed using typical parameters of two integrated circuit fabrication processes (N-well Austriamicrosystems 0.35 μm CMOS and Berkeley 0.13 μm) are presented. Based on the experimental results obtained from local and global clock distribution networks fabricated in Austriamicrosystems 0.35 μm process, it was demonstrated that the interconnected and coupled ring oscillators represent a good approach for integrated systems in a single silicon chip due to its good performance, scalability with technology, low time uncertainty, high speed, fault tolerance, and robustness to process variations.

Article

Circuitos integrados Osciladores Redes de reloj Sincronización Integrated circuits Oscillators Clock networks Synchronization CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA FÍSICA ELECTRÓNICA ELECTRÓNICA