Título

CMOS full-adders for energy-efficient arithmetic applications

Autor

MARIANO AGUIRRE HERNANDEZ

MONICO LINARES ARANDA

Nivel de Acceso

Acceso Abierto

Licencia

http://creativecommons.org/licenses/by-nc-nd/4.0

Materias

Arithmetic - (ARITHMETIC) Full-adder - (FULL-ADDER) High-speed - (HIGH-SPEED) Low-power - (LOW-POWER) CIENCIAS FÍSICO MATEMÁTICAS Y CIENCIAS DE LA TIERRA - (CTI) FÍSICA - (CTI) ELECTRÓNICA - (CTI) ELECTRÓNICA - (CTI)

Resumen o descripción

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

Editor

IEEE

Fecha de publicación

2011

Tipo de publicación

Artículo

Versión de la publicación

Versión aceptada

Recurso de información

http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/1740

Formato

application/pdf

Idioma

Inglés

Relación

&

Linares-Aranda, M. (2011). CMOS full-adders for energy-efficient arithmetic applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, (4): 718-721

Audiencia

Estudiantes

Investigadores

Público en general

Sugerencia de citación

Aguirre-Hernandez, M.

Repositorio Orígen

Repositorio Institucional del INAOE

Descargas

273