Title

CMOS full-adders for energy-efficient arithmetic applications

Author

MARIANO AGUIRRE HERNANDEZ

MONICO LINARES ARANDA

Access level

Open Access

Summary or description

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

Publisher

IEEE

Publish date

2011

Publication type

Article

Publication version

Accepted Version

Format

application/pdf

Language

English

Relation

&

Linares-Aranda, M. (2011). CMOS full-adders for energy-efficient arithmetic applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, (4): 718-721

Audience

Students

Researchers

General public

Citation suggestion

Aguirre-Hernandez, M.

Source repository

Repositorio Institucional del INAOE

Downloads

78

Comments



You need to sign in or sign up to comment.